Uniication of Register Allocation and Instruction Scheduling in Compilers for Fine-grain Parallel Architectures Unification of Register Allocation and Instruction Scheduling in Compilers for Fine-grain Parallel Architectures

The interaction between instruction scheduling and register allocation has signiicant impact on the quality of code generated, particularly in compilers targeting ne grain parallel architectures. The problem results from the fact that instruction scheduling and register allocation have connicting goals. Instruction scheduling tries to maximize parallelism by scheduling as many instructions as possible in parallel, which requires a large number of values to be held in registers for short periods of time. On the other hand, register allocation attempts to hold a small number of values in registers for long periods of time, resulting in limiting the number of instructions that can be scheduled in parallel. This dissertation presents a method for unifying these tasks by allocating all needed registers and functional units to an instruction simultaneously. No previous technique has achieved this degree of integration between the two tasks. The work in this dissertation is based on a framework consisting of three components: a technique for measuring a program's demand for all resources, a single intermediate representation of the measured demands, and a set of transformations that perform resource allocation. The approach taken in this work is based on a new paradigm of resource allocation, called Measure and Reduce in which the resource requirements of the program are measured and excessive demands are removed by reduction transformations. The information computed during the measurement of the demands for each resource is incorporated into a single intermediate representation. The reduction transformations for all resources operate on this intermediate representation, allowing transformations for diierent types of resources to be performed simultaneously. Therefore, an instruction can be allocated all resources it needs at once, resulting in uniied resource allocation. The intermediate representation is based on a hierarchical form of dependence DAGs, enabling the transformations to naturally handle instruction level parallelism. In particular, the register transformations form a framework for live range splitting in the absence of a full ordering of the instructions, as required by previous splitting techniques. Application of the reduction transformations is rst demonstrated by a heuristic for performing register allocation during local instruction scheduling. Global register allocation is performed by exploiting the hierarchical nature of the intermediate representation. Heuristics are also given for using the transformations during global code motion, resulting in uniied allocation and a more exible use of available resources than previous resource constrained techniques. The results of numerous experiments comparing the new techniques to previous attempts at …